AI Boom Turns Chip Packaging Into Next Semiconductor Battleground

A global race to build AI infrastructure is unleashing billions of dollars of investment in advanced chip packaging, a once unglamorous step that has become a critical bottleneck in turning out the world's most powerful processors, Reuters reported on Nov. 6.

As demand for AI chips outstrips available packaging capacity, companies from Nvidia (NVDA) and AMD (AMD) to lesser-known suppliers in Taiwan are expanding production, while equipment makers develop new tools, according to interviews with more than a dozen industry executives and analysts.

Revenue from advanced packaging is forecast to overtake that earned via the traditional route for the first time in 2026, research firm Yole Group said, with capital spending on the technology expected to near $28 billion.

TSMC leads, but capacity is tight

Taiwan Semiconductor Manufacturing (TSM), the world's largest contract chipmaker, dominates the most sophisticated advanced packaging technology, including chip-on-wafer-on-substrate, or CoWoS. The technique links separate pieces of silicon, such as processors and memory chips, on a shared base so they work together at high speed. It is widely used by Nvidia, AMD and Broadcom (AVGO), as well as cloud companies building their own AI chips.

But TSMC's capacity limits have spurred some chip designers to seek additional supply. Nvidia is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries, or SPIL, a unit of Taiwan's ASE Technology, an industry executive familiar with the matter told Reuters. The funding will support new factory space and equipment; Nvidia and ASE declined to comment, and the scale of the support had not previously been reported.

A race for TSMC alternatives

TSMC's tight capacity offers an opening for smaller suppliers. Powertech Technology, also known as PTI, is betting on panel-level packaging, which uses larger rectangular panels instead of round wafers and can accommodate more chips per production run with less waste. PTI is working with AMD and Broadcom on the technology.

Powertech chairman D K Tsai told reporters in August that everyone is looking for a solution outside TSMC and that they do not want to rely entirely on TSMC.

Powertech plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore, with production possible from 2028. TSMC is developing its own panel-based technology, called chip-on-panel-on-substrate, or CoPoS; in April it said it had built a pilot line and expected production to begin within a couple of years, though CoWoS remains its main AI-packaging technology.

Equipment makers join the rush

The packaging boom is opening a new market for semiconductor equipment makers, which have traditionally focused on earlier stages of chipmaking. Advanced packaging was growing much faster than the market for chip-making gear, though it remained smaller, said Seiji Nakama, president of Tokyo Electron Taiwan. The market for advanced packaging, including panel-level technology, could grow significantly within three to five years, said Sree Kesapragada, a vice president at Applied Materials.

AMD chief executive Lisa Su told Reuters in Taipei in October that CoWoS and advanced packaging are super important for high-performance computing going forward, and that more capacity is needed overall.

In delayed trading, Nvidia shares were up 2.78%, AMD up 11.04%, Broadcom up 0.74% and TSMC up 6.33%.

What is known: TSMC dominates CoWoS and capacity is tight, while alternatives are being developed. What remains unclear is how quickly panel-level packaging can scale and whether it can match TSMC's yields for the largest AI packages. The next dated milestone is Powertech's Singapore production, which could begin in 2028.